Design and Performance Analysis of Improved FIR Filter using Ultra-Scale FPGA

Bhagwan Das; Javed Ali; Mahendar Kumar; Dileep Kumar; Muhammad Zakir Shaikh

Authors

Bhagwan Das QUAID-E-AWAM UNIVERSITY OF ENGINEERING, SCIENCE AND TECHNOLOGY, PAKISTAN
Javed Ali
Mahendar Kumar
Dileep Kumar
Muhammad Zakir Shaikh

Keywords:

CSD Technique, Digital Filter Design, Filter Response, Response Rate, UltraScale FPGA

Abstract

It is discussed in many studies and demonstrated in many pieces of research that based on certain applications, analog design of filter has several issues including complex design, re-use limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design, the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital Finite Impulse Response (FIR) filter designed is demonstrated using Ultra-Scale Field Programming Gate Array (FPGA) having chip XCKU3P. The filter is designed using a coefficient multiplier via Canonic Signed Digit (CSD) Technique. The optimized design of the digital filter is conducted via real-time implementation is performed using Ultra-Scale FPGA. The filter is designed and evaluated with an ordinary filter at 10 MHz and 10 GHz frequencies. The performance analysis of the system is illustrated using the response rate at the bitstream of 16-bit. In the results, it is demonstrated that for 10 MHz frequency design FIR filter in FPGA the 30% faster response filter is achieved at for 10 GHz, the 15% faster response is achieved at the I/O standard of Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS). The optimization of 30% in terms of the response time of the filter is attained using the proposed work. The proposed improved FIR filter design using Ultra-Scale FPGA helps in increasing design performance to increase the speed of overall response of FIR filter that is lacking in ordinary Filters.

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